1. Field of the Invention
The present invention relates to a semiconductor wafer and a manufacturing method for a semiconductor device, and in particular, to a technique for preventing peeling-off of a film and pattern skipping in an end portion, i.e., a wafer edge portion, of a semiconductor substrate.
2. Description of the Background Art
In recent years, the reduction in element size has progressed and the dimensions of interconnect lines and vias have also been reduced. In order to increase the speed of elements, the demand for films with lower resistance and lower capacitance has increased in multilayer interconnections. Low-k films (low dielectric constant films), such as SiOC, ULK, and ELK with low dielectric constants (k), are now being used as interlayer films in multilayer. Such semiconductor wafers and their manufacturing methods are disclosed in, for example, Japanese Patent Application Laid-Open Nos. 2005-217319, 2003-78005, 2003-17559, and 2006-147681.
Japanese Patent Application Laid-Open No. 2005-217319, for example, discloses an invention that relates to a manufacturing method for a semiconductor device with Cu damascene multilayer interconnections using low dielectric constant films as interlayer films, wherein the degree in which the low dielectric constant interlayer films are backed off from the periphery is made different for each layer in the periphery of the wafer as a measure against peeling-off during CMP.
Japanese Patent Application Laid-Open No. 2003-78005, for example, discloses an invention that relates to a manufacturing method for a semiconductor device having multilayer interconnections using Low-k films as interlayer films, wherein the edges of the Low-k films are cut at the wafer edge.
Japanese Patent Application Laid-Open No. 2003-17559, for example, discloses an invention that relates to a manufacturing method for a semiconductor device with a multilayer interconnection structure using low dielectric constant interlayer films of Cu damascene interconnect lines, wherein the peripheral structure is such that low dielectric constant interlayer films are backed off from the wafer edge so as to be covered with an insulating film in ordinary circumstances.
Japanese Patent Application Laid-Open No. 2006-147681, for example, discloses an invention that relates to a manufacturing method for a semiconductor device with a multilayer interconnection structure using low dielectric constant films as interlayer films, wherein the structure is such that the low dielectric constant films are etched back from the wafer edge portion so as to be covered with an insulating film in ordinary circumstances.
Problems to be solved by the present invention are given in the following description by citing the case of a DD (dual damascene) procedure where Low-k films (SiOC, ULK, ELK; k≦3.0) are employed as Fine interlayer film layers (Mx, Vx) having the smallest dimensions.
In this case, the Fine interlayer films as the Low-k films have low strength and weak adhesion, and due to such stresses, they may peel off from the wafer edge portion during the lamination, which can undesirably cause a reduction in yield or the like.
There is also a problem that foreign matter resulting from the process (such as slurry residues after polishing) may exist in areas of the wafer edge portion where plating cannot be applied, which can cause a reduction in yield or the like.
In order to solve the problems, a technique for removing all interlayer films including a contact interlayer film from the wafer edge portion has been suggested. This technique, however, has a drawback that a barrier metal is deposited directly on the silicon substrate in the wafer edge portion so that, in subsequent processes, the films may peel off due to stresses caused mainly by heat treatment.
To avoid such a problem, another technique for removing all interlayer films except for the contact interlayer film from the wafer edge portion, i.e., not removing the contact interlayer film, has been suggested. As a result, a barrier metal, e.g., Ta, is not directly deposited on the silicon substrate in the wafer edge portion during a Cu process so that it is possible to prevent peeling-off of films in subsequent processes.
However, even if the contact interlayer film is intentionally left in such a manner, it may completely be removed by etching when a multilayer interconnection structure is formed by removal of the wafer edge in a via process and in an interconnection process during a dual damascene (DD) procedure. In this case, such a problem arises that a barrier metal, e.g., Ta, is directly deposited on the silicon substrate in the wafer edge portion during the Cu process, which can cause peeling-off of films.